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Phase Lock Basics Egan.pdf

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Few topics in electrical engineering have demanded as much attention over the years as the phase-locked loop (PLL). The PLL is arguably one of the most important building blocks necessary for modern digital communications, whether in the RF radio portion of the hardware where it is used to synthesize pristine carrier signals, or in the baseband digital signal processing (DSP) where it is often used for carrier- and time-recovery processing. The PLL topic is also intriguing because a thorough understanding of the concept embraces ingredients from many disciplines including RF design, digital design, continuous and discrete-time control systems, estimation theory and communication theory.

"The phase-lock concept as we know it today was originally described in a published work by de Bellescize in 19321 but did not fall into widespread use until the era of television where it was used to synchronize horizontal and vertical video scans. One of the earliest patents showing the use of a PLL with a feedback divider for frequency synthesis appeared in 1970.2 The PLL concept is now used almost universally in many products ranging from citizens band radio to deep-space coherent receivers."1

In a similar fashion, different analysis must be used to study PLL operation under low signal-to-noise ratio (SNR) cases (e.g., customarily found in receiver applications) as compared to high SNR cases (e.g., like those encountered in frequency synthesizer usage). Several different perspectives that all help expand the phase-locked loop concept are discussed in the material that follows.

where s(t)= A cos(ωot + θ) and the frequency and phase are considered constant. In the phase-lock condition, we can further assume that the frequency ωo is known whereas the system is attempting to track the phase θ, which is assumed to be quasi-static relative to the bandwidth of the PLL tracking system. It can be shown that the probability density function for the θ estimate can be written as: 153554b96e

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